Integrated circuits (ICs) utilize output buffers for driving the output signaling through a transmission medium (such as traces on a circuit board) and through the load of the destination circuit. Output buffers are generally comprised of pads that form the external electronic connection mechanism and drivers that supply other output power for an output signal. The design of output buffers should address waveshaping, load handling, switching speed, and reliability concerns. It is generally desirable for high speed, resistively terminated, output buffers to satisfy two design criteria for optimum performance. First, the output resistance should match the characteristic impedance of the transmission medium. Second, the output buffer's switching speed, or slew rate, should be as slow as tolerable so as to minimize reflections and electromagnetic interference (EMI), yet still fast enough to fully switch between high and low logic levels during the data setup time durations between sampling events at the destination circuit.
Known approaches for controlling the slew rate of common mode logic (CML) type output buffers include complicated designs and implemtations, including rapid, sequential switching between small output drivers connected in parallel to a single pad. Complex designs with small feature sizes are susceptible to manufacturing defects 7 that reduce production yield and increase device cost. Small device features in output pads are also susceptible to electrostatic discharge (ESD) and other fast transient phenomena, which also adversely affect manufacturing yield, but also result in field failures including sleeping (latent) failures.
An output buffer circuit and method that addresses these, and other problems, is therefore desirable.